//============================================
// Define VDD and VSS
//============================================
VVDD (VDD 0) vsource dc=pvdd
VVDDC (VDDC 0) vsource dc=pvddc
VVDDR (VDDR 0) vsource dc=pvdd
VVDD2 (VDD2 0) vsource dc=pvdd
VVSS (VSS 0) vsource dc=0
VVBP (VBP 0) vsource dc=pvbp
VVBPC (VBPC 0) vsource dc=pvddc
VVBN (VBN 0) vsource dc=pvbn

VIN (IN 0) vsource type=pulse val0=0 val1=pvdd rise=prise fall=pfall width=pwidth period=pper

//Inverter
subckt Inv (Input Output VDD VSS VBN VBP)
P1 (VDD Input Output VBP) P_TRANSISTOR width=wp length=ldef
N1 (VSS Input Output VBN) N_TRANSISTOR width=wn length=ldef
ends Inv

subckt Inv2x (Input Output VDD VSS VBN VBP)
P1 (VDD Input Output VBP) P_TRANSISTOR width=2*wp length=ldef
N1 (VSS Input Output VBN) N_TRANSISTOR width=2*wn length=ldef
ends Inv2x

//Driver
subckt Driver (Input Output VDD VSS VBN VBP)
P1 (VDD Input A VBP) P_TRANSISTOR width=10*wp length=ldef
N1 (VSS Input A VBN) N_TRANSISTOR width=10*wn length=ldef
P2 (VDD A Output VBP) P_TRANSISTOR width=10*wp length=ldef
N2 (VSS A Output VBN) N_TRANSISTOR width=10*wn length=ldef
ends Driver

//Buffer
subckt Buffer (Input Output VDD VSS VBN VBP)
P1 (A Input VDD VBP) P_TRANSISTOR width=wp length=ldef
N1 (A Input VSS VBN) N_TRANSISTOR width=wn length=ldef
P2 (Output A VDD VBP) P_TRANSISTOR width=wp length=ldef
N2 (Output A VSS VBN) N_TRANSISTOR width=wn length=ldef
ends Buffer

//Switch (Pass Gate)
subckt PGSwitch (Input Output VDD VDDc VSS VBN VBP)
N (Input VDDc Output VBN) N_TRANSISTOR width=wn length=ldef
ends PGSwitch

//Switch (Transmission Gate)
subckt TXSwitch (Input Output VDD VDDc VSS VBN VBP)
N (Input VDDc Output VBN) N_TRANSISTOR width=wn length=ldef
P (Input VSS Output VBP) P_TRANSISTOR width=wp length=ldef
ends TXSwitch

//Switch (Tri-State Buffer)
subckt TSSwitch (Input Output VDD VDDc VSS VBN VBP)
P1 (A Input VDD VBP) P_TRANSISTOR width=5*wp length=ldef
N1 (A Input VSS VBN) N_TRANSISTOR width=5*wn length=ldef
P2 (B A VDD VBP) P_TRANSISTOR width=5*wp length=ldef
N2 (B A VSS VBN) N_TRANSISTOR width=5*wn length=ldef
NC (B VDDc Output VBN) N_TRANSISTOR width=wn length=ldef
ends TSSwitch

//Switchbox
subckt Switchbox (Input Output VDD VDDc VSS VBN VBP VBPC)
S1 (Input A VDD Bit1 VSS VBN VBP) TSSwitch
Soff1 (Input off1 VDD Bit2 VSS VBN VBP) TSSwitch
Soff2 (Input off2 VDD Bit3 VSS VBN VBP) TSSwitch
Soff3 (A off3 VDD Bit4 VSS VBN VBP) TSSwitch
Soff4 (A off4 VDD Bit5 VSS VBN VBP) TSSwitch
bcell1 (Bit1 VSS VDDc VSS VBN VBPC) bitcell
bcell2 (Bit2 VDD VDDc VSS VBN VBPC) bitcell
bcell3 (Bit3 VDD VDDc VSS VBN VBPC) bitcell
bcell4 (Bit4 VDD VDDc VSS VBN VBPC) bitcell
bcell5 (Bit5 VDD VDDc VSS VBN VBPC) bitcell
R (A Output) resistor r=50
C (Output VSS) capacitor c=13f
Roff1 (off1 off_1) resistor r=50
Coff1 (off_1 VSS) capacitor c=13f
Roff2 (off2 off_2) resistor r=50
Coff2 (off_2 VSS) capacitor c=13f
Roff3 (off3 off_3) resistor r=50
Coff3 (off_3 VSS) capacitor c=13f
Roff4 (off4 off_4) resistor r=50
Coff4 (off_4 VSS) capacitor c=13f
ends Switchbox

//LUT
subckt LUT (in1 in2 in3 in4 out VDD VSS VBN VBP)

cell1 (val1 VSS VDD VSS VBN VBP) bitcell
cell2 (val2 VDD VDD VSS VBN VBP) bitcell
cell3 (val3 VDD VDD VSS VBN VBP) bitcell
cell4 (val4 VSS VDD VSS VBN VBP) bitcell
cell5 (val5 VSS VDD VSS VBN VBP) bitcell
cell6 (val6 VDD VDD VSS VBN VBP) bitcell
cell7 (val7 VDD VDD VSS VBN VBP) bitcell
cell8 (val8 VSS VDD VSS VBN VBP) bitcell
cell9 (val9 VSS VDD VSS VBN VBP) bitcell
cell10 (val10 VDD VDD VSS VBN VBP) bitcell
cell11 (val11 VDD VDD VSS VBN VBP) bitcell
cell12 (val12 VSS VDD VSS VBN VBP) bitcell
cell13 (val13 VSS VDD VSS VBN VBP) bitcell
cell14 (val14 VDD VDD VSS VBN VBP) bitcell
cell15 (val15 VDD VDD VSS VBN VBP) bitcell
cell16 (val16 VSS VDD VSS VBN VBP) bitcell

LB1 (in1 en1 en1b VDD VSS VBN VBP) LUTBuff
LB2 (in2 en2 en2b VDD VSS VBN VBP) LUTBuff
LB3 (in3 en3 en3b VDD VSS VBN VBP) LUTBuff
LB4 (in4 en4 en4b VDD VSS VBN VBP) LUTBuff

Mux (val1 val2 val3 val4 val5 val6 val7 val8 val9 val10 val11 val12 val13 val14 val15 val16 out en1 en1b en2 en2b en3 en3b en4 en4b vbn) Mux16_1

ends LUT

subckt LUTBuff (in out outb vdd vss vbn vbp)
i1 (in a vdd vss vbn vbp) Inv
i2 (a out vdd vss vbn vbp) Inv2x
i3 (in outb vdd vss vbn vbp) Inv2x
ends LUTBuff

//Muxes
subckt Mux2_1 (in1 in2 out en enb VBN)
S1 (in1 en out VBN) N_TRANSISTOR width=wn length=ldef
S2 (in2 enb out VBN) N_TRANSISTOR width=wn length=ldef
ends Mux2_1

subckt Mux4_1 (in1 in2 in3 in4 out en1 en1b en2 en2b vbn)
M1 (in1 in2 out1 en1 en1b vbn) Mux2_1
M2 (in3 in4 out2 en1 en1b vbn) Mux2_1
M3 (out1 out2 out en2 en2b vbn) Mux2_1
ends Mux4_1

subckt Mux8_1 (in1 in2 in3 in4 in5 in6 in7 in8 out en1 en1b en2 en2b en3 en3b vbn)
M1 (in1 in2 in3 in4 out1 en1 en1b en2 en2b vbn) Mux4_1
M2 (in5 in6 in7 in8 out2 en1 en1b en2 en2b vbn) Mux4_1
M3 (out1 out2 out en3 en3b vbn) Mux2_1
ends Mux8_1

subckt Mux16_1 (in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 in11 in12 in13 in14 in15 in16 out en1 en1b en2 en2b en3 en3b en4 en4b vbn)
M1 (in1 in2 in3 in4 in5 in6 in7 in8 out1 en1 en1b en2 en2b en3 en3b vbn) Mux8_1
M2 (in9 in10 in11 in12 in13 in14 in15 in16 out2 en1 en1b en2 en2b en3 en3b vbn) Mux8_1
M3 (out1 out2 out en4 en4b vbn) Mux2_1
ends Mux16_1

subckt Mux14_1 (in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 in11 in12 in13 in14 out en1 en1b en2 en2b en3 en3b en4 en4b vbn)
M1 (in1 in2 in3 in4 in5 in6 in7 in8 out1 en1 en1b en2 en2b en3 en3b vbn) Mux8_1
M2 (in9 in10 in11 in12 out2 en1 en1b en2 en2b vbn) Mux4_1
M3 (in13 in14 out3 en1 en1b vbn) Mux2_1
M4 (out2 out3 out4 en3 en3b vbn) Mux2_1
M5 (out1 out4 out en4 en4b vbn) Mux2_1
ends Mux14_1

//CLB
subckt CLB_N4 (in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 out1 out2 out3 out4 VDD VSS VBN VBP)//10 inputs, 4 outputs, 4 LUTs
//BLE1
M1_1 (in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 out1 out2 out3 out4 ble1_in1 ble1_in1_en1 ble1_in1_en1b ble1_in1_en2 ble1_in1_en2b ble1_in1_en3 ble1_in1_enb ble1_in1_en4 ble1_in1_en4b vbn) Mux14_1

M1_2 (in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 out1 out2 out3 out4 ble1_in2 ble1_in2_en1 ble1_in2_en1b ble1_in2_en2 ble1_in2_en2b ble1_in2_en3 ble1_in2_enb ble1_in2_en4 ble1_in2_en4b vbn) Mux14_1

M1_3 (in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 out1 out2 out3 out4 ble1_in3 ble1_in3_en1 ble1_in3_en1b ble1_in3_en2 ble1_in3_en2b ble1_in3_en3 ble1_in3_enb ble1_in3_en4 ble1_in3_en4b vbn) Mux14_1

M1_4 (in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 out1 out2 out3 out4 ble1_in4 ble1_in4_en1 ble1_in4_en1b ble1_in4_en2 ble1_in4_en2b ble1_in4_en3 ble1_in4_enb ble1_in4_en4 ble1_in4_en4b vbn) Mux14_1

L1 (ble1_in1 ble1_in2 ble1_in3 ble1_in4 out1 VDD VSS VBN VBP)

//BLE2
M2_1 (in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 out1 out2 out3 out4 ble2_in1 ble2_in1_en1 ble2_in1_en1b ble2_in1_en2 ble2_in1_en2b ble2_in1_en3 ble2_in1_enb ble2_in1_en4 ble2_in1_en4b vbn) Mux14_1

M2_2 (in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 out1 out2 out3 out4 ble2_in2 ble2_in2_en1 ble2_in2_en1b ble2_in2_en2 ble2_in2_en2b ble2_in2_en3 ble2_in2_enb ble2_in2_en4 ble2_in2_en4b vbn) Mux14_1

M2_3 (in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 out1 out2 out3 out4 ble2_in3 ble2_in3_en1 ble2_in3_en1b ble2_in3_en2 ble2_in3_en2b ble2_in3_en3 ble2_in3_enb ble2_in3_en4 ble2_in3_en4b vbn) Mux14_1

M2_4 (in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 out1 out2 out3 out4 ble2_in4 ble2_in4_en1 ble2_in4_en1b ble2_in4_en2 ble2_in4_en2b ble2_in4_en3 ble2_in4_enb ble2_in4_en4 ble2_in4_en4b vbn) Mux14_1

L2 (ble2_in1 ble2_in2 ble2_in3 ble2_in4 out2 VDD VSS VBN VBP)

//ble3
M3_1 (in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 out1 out2 out3 out4 ble3_in1 ble3_in1_en1 ble3_in1_en1b ble3_in1_en2 ble3_in1_en2b ble3_in1_en3 ble3_in1_enb ble3_in1_en4 ble3_in1_en4b vbn) Mux14_1

M3_2 (in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 out1 out2 out3 out4 ble3_in2 ble3_in2_en1 ble3_in2_en1b ble3_in2_en2 ble3_in2_en2b ble3_in2_en3 ble3_in2_enb ble3_in2_en4 ble3_in2_en4b vbn) Mux14_1

M3_3 (in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 out1 out2 out3 out4 ble3_in3 ble3_in3_en1 ble3_in3_en1b ble3_in3_en2 ble3_in3_en2b ble3_in3_en3 ble3_in3_enb ble3_in3_en4 ble3_in3_en4b vbn) Mux14_1

M3_4 (in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 out1 out2 out3 out4 ble3_in4 ble3_in4_en1 ble3_in4_en1b ble3_in4_en2 ble3_in4_en2b ble3_in4_en3 ble3_in4_enb ble3_in4_en4 ble3_in4_en4b vbn) Mux14_1

L3 (ble3_in1 ble3_in2 ble3_in3 ble3_in4 out3 VDD VSS VBN VBP)

//ble4
M4_1 (in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 out1 out2 out3 out4 ble4_in1 ble4_in1_en1 ble4_in1_en1b ble4_in1_en2 ble4_in1_en2b ble4_in1_en3 ble4_in1_enb ble4_in1_en4 ble4_in1_en4b vbn) Mux14_1

M4_2 (in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 out1 out2 out3 out4 ble4_in2 ble4_in2_en1 ble4_in2_en1b ble4_in2_en2 ble4_in2_en2b ble4_in2_en3 ble4_in2_enb ble4_in2_en4 ble4_in2_en4b vbn) Mux14_1

M4_3 (in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 out1 out2 out3 out4 ble4_in3 ble4_in3_en1 ble4_in3_en1b ble4_in3_en2 ble4_in3_en2b ble4_in3_en3 ble4_in3_enb ble4_in3_en4 ble4_in3_en4b vbn) Mux14_1

M4_4 (in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 out1 out2 out3 out4 ble4_in4 ble4_in4_en1 ble4_in4_en1b ble4_in4_en2 ble4_in4_en2b ble4_in4_en3 ble4_in4_enb ble4_in4_en4 ble4_in4_en4b vbn) Mux14_1

L4 (ble4_in1 ble4_in2 ble4_in3 ble4_in4 out4 VDD VSS VBN VBP) LUT

//bitcells
bcell_ble1_in1_en1 (ble1_in1_en1 VSS VDD VSS VBN VBP) bitcell
bcell_ble1_in1_en1b (ble1_in1_en1b VDD VDD VSS VBN VBP) bitcell

bcell_ble1_in1_en2 (ble1_in1_en2 VSS VDD VSS VBN VBP) bitcell
bcell_ble1_in1_en2b (ble1_in1_en2b VDD VDD VSS VBN VBP) bitcell

bcell_ble1_in1_en3 (ble1_in1_en3 VSS VDD VSS VBN VBP) bitcell
bcell_ble1_in1_en3b (ble1_in1_en3b VDD VDD VSS VBN VBP) bitcell

bcell_ble1_in1_en4 (ble1_in1_en4 VSS VDD VSS VBN VBP) bitcell
bcell_ble1_in1_en4b (ble1_in1_en4b VDD VDD VSS VBN VBP) bitcell

bcell_ble1_in2_en1 (ble1_in2_en1 VSS VDD VSS VBN VBP) bitcell
bcell_ble1_in2_en1b (ble1_in2_en1b VDD VDD VSS VBN VBP) bitcell

bcell_ble1_in2_en2 (ble1_in2_en2 VSS VDD VSS VBN VBP) bitcell
bcell_ble1_in2_en2b (ble1_in2_en2b VDD VDD VSS VBN VBP) bitcell

bcell_ble1_in2_en3 (ble1_in2_en3 VSS VDD VSS VBN VBP) bitcell
bcell_ble1_in2_en3b (ble1_in2_en3b VDD VDD VSS VBN VBP) bitcell

bcell_ble1_in2_en4 (ble1_in2_en4 VSS VDD VSS VBN VBP) bitcell
bcell_ble1_in2_en4b (ble1_in2_en4b VDD VDD VSS VBN VBP) bitcell

bcell_ble1_in3_en1 (ble1_in3_en1 VSS VDD VSS VBN VBP) bitcell
bcell_ble1_in3_en1b (ble1_in3_en1b VDD VDD VSS VBN VBP) bitcell

bcell_ble1_in3_en2 (ble1_in3_en2 VSS VDD VSS VBN VBP) bitcell
bcell_ble1_in3_en2b (ble1_in3_en2b VDD VDD VSS VBN VBP) bitcell

bcell_ble1_in3_en3 (ble1_in3_en3 VSS VDD VSS VBN VBP) bitcell
bcell_ble1_in3_en3b (ble1_in3_en3b VDD VDD VSS VBN VBP) bitcell

bcell_ble1_in3_en4 (ble1_in3_en4 VSS VDD VSS VBN VBP) bitcell
bcell_ble1_in3_en4b (ble1_in3_en4b VDD VDD VSS VBN VBP) bitcell

bcell_ble1_in4_en1 (ble1_in4_en1 VSS VDD VSS VBN VBP) bitcell
bcell_ble1_in4_en1b (ble1_in4_en1b VDD VDD VSS VBN VBP) bitcell

bcell_ble1_in4_en2 (ble1_in4_en2 VSS VDD VSS VBN VBP) bitcell
bcell_ble1_in4_en2b (ble1_in4_en2b VDD VDD VSS VBN VBP) bitcell

bcell_ble1_in4_en3 (ble1_in4_en3 VSS VDD VSS VBN VBP) bitcell
bcell_ble1_in4_en3b (ble1_in4_en3b VDD VDD VSS VBN VBP) bitcell

bcell_ble1_in4_en4 (ble1_in4_en4 VSS VDD VSS VBN VBP) bitcell
bcell_ble1_in4_en4b (ble1_in4_en4b VDD VDD VSS VBN VBP) bitcell

bcell_ble2_in1_en1 (ble2_in1_en1 VSS VDD VSS VBN VBP) bitcell
bcell_ble2_in1_en1b (ble2_in1_en1b VDD VDD VSS VBN VBP) bitcell

bcell_ble2_in1_en2 (ble2_in1_en2 VSS VDD VSS VBN VBP) bitcell
bcell_ble2_in1_en2b (ble2_in1_en2b VDD VDD VSS VBN VBP) bitcell

bcell_ble2_in1_en3 (ble2_in1_en3 VSS VDD VSS VBN VBP) bitcell
bcell_ble2_in1_en3b (ble2_in1_en3b VDD VDD VSS VBN VBP) bitcell

bcell_ble2_in1_en4 (ble2_in1_en4 VSS VDD VSS VBN VBP) bitcell
bcell_ble2_in1_en4b (ble2_in1_en4b VDD VDD VSS VBN VBP) bitcell

bcell_ble2_in2_en1 (ble2_in2_en1 VSS VDD VSS VBN VBP) bitcell
bcell_ble2_in2_en1b (ble2_in2_en1b VDD VDD VSS VBN VBP) bitcell

bcell_ble2_in2_en2 (ble2_in2_en2 VSS VDD VSS VBN VBP) bitcell
bcell_ble2_in2_en2b (ble2_in2_en2b VDD VDD VSS VBN VBP) bitcell

bcell_ble2_in2_en3 (ble2_in2_en3 VSS VDD VSS VBN VBP) bitcell
bcell_ble2_in2_en3b (ble2_in2_en3b VDD VDD VSS VBN VBP) bitcell

bcell_ble2_in2_en4 (ble2_in2_en4 VSS VDD VSS VBN VBP) bitcell
bcell_ble2_in2_en4b (ble2_in2_en4b VDD VDD VSS VBN VBP) bitcell

bcell_ble2_in3_en1 (ble2_in3_en1 VSS VDD VSS VBN VBP) bitcell
bcell_ble2_in3_en1b (ble2_in3_en1b VDD VDD VSS VBN VBP) bitcell

bcell_ble2_in3_en2 (ble2_in3_en2 VSS VDD VSS VBN VBP) bitcell
bcell_ble2_in3_en2b (ble2_in3_en2b VDD VDD VSS VBN VBP) bitcell

bcell_ble2_in3_en3 (ble2_in3_en3 VSS VDD VSS VBN VBP) bitcell
bcell_ble2_in3_en3b (ble2_in3_en3b VDD VDD VSS VBN VBP) bitcell

bcell_ble2_in3_en4 (ble2_in3_en4 VSS VDD VSS VBN VBP) bitcell
bcell_ble2_in3_en4b (ble2_in3_en4b VDD VDD VSS VBN VBP) bitcell

bcell_ble2_in4_en1 (ble2_in4_en1 VSS VDD VSS VBN VBP) bitcell
bcell_ble2_in4_en1b (ble2_in4_en1b VDD VDD VSS VBN VBP) bitcell

bcell_ble2_in4_en2 (ble2_in4_en2 VSS VDD VSS VBN VBP) bitcell
bcell_ble2_in4_en2b (ble2_in4_en2b VDD VDD VSS VBN VBP) bitcell

bcell_ble2_in4_en3 (ble2_in4_en3 VSS VDD VSS VBN VBP) bitcell
bcell_ble2_in4_en3b (ble2_in4_en3b VDD VDD VSS VBN VBP) bitcell

bcell_ble2_in4_en4 (ble2_in4_en4 VSS VDD VSS VBN VBP) bitcell
bcell_ble2_in4_en4b (ble2_in4_en4b VDD VDD VSS VBN VBP) bitcell

bcell_ble3_in1_en1 (ble3_in1_en1 VSS VDD VSS VBN VBP) bitcell
bcell_ble3_in1_en1b (ble3_in1_en1b VDD VDD VSS VBN VBP) bitcell

bcell_ble3_in1_en2 (ble3_in1_en2 VSS VDD VSS VBN VBP) bitcell
bcell_ble3_in1_en2b (ble3_in1_en2b VDD VDD VSS VBN VBP) bitcell

bcell_ble3_in1_en3 (ble3_in1_en3 VSS VDD VSS VBN VBP) bitcell
bcell_ble3_in1_en3b (ble3_in1_en3b VDD VDD VSS VBN VBP) bitcell

bcell_ble3_in1_en4 (ble3_in1_en4 VSS VDD VSS VBN VBP) bitcell
bcell_ble3_in1_en4b (ble3_in1_en4b VDD VDD VSS VBN VBP) bitcell

bcell_ble3_in2_en1 (ble3_in2_en1 VSS VDD VSS VBN VBP) bitcell
bcell_ble3_in2_en1b (ble3_in2_en1b VDD VDD VSS VBN VBP) bitcell

bcell_ble3_in2_en2 (ble3_in2_en2 VSS VDD VSS VBN VBP) bitcell
bcell_ble3_in2_en2b (ble3_in2_en2b VDD VDD VSS VBN VBP) bitcell

bcell_ble3_in2_en3 (ble3_in2_en3 VSS VDD VSS VBN VBP) bitcell
bcell_ble3_in2_en3b (ble3_in2_en3b VDD VDD VSS VBN VBP) bitcell

bcell_ble3_in2_en4 (ble3_in2_en4 VSS VDD VSS VBN VBP) bitcell
bcell_ble3_in2_en4b (ble3_in2_en4b VDD VDD VSS VBN VBP) bitcell

bcell_ble3_in3_en1 (ble3_in3_en1 VSS VDD VSS VBN VBP) bitcell
bcell_ble3_in3_en1b (ble3_in3_en1b VDD VDD VSS VBN VBP) bitcell

bcell_ble3_in3_en2 (ble3_in3_en2 VSS VDD VSS VBN VBP) bitcell
bcell_ble3_in3_en2b (ble3_in3_en2b VDD VDD VSS VBN VBP) bitcell

bcell_ble3_in3_en3 (ble3_in3_en3 VSS VDD VSS VBN VBP) bitcell
bcell_ble3_in3_en3b (ble3_in3_en3b VDD VDD VSS VBN VBP) bitcell

bcell_ble3_in3_en4 (ble3_in3_en4 VSS VDD VSS VBN VBP) bitcell
bcell_ble3_in3_en4b (ble3_in3_en4b VDD VDD VSS VBN VBP) bitcell

bcell_ble3_in4_en1 (ble3_in4_en1 VSS VDD VSS VBN VBP) bitcell
bcell_ble3_in4_en1b (ble3_in4_en1b VDD VDD VSS VBN VBP) bitcell

bcell_ble3_in4_en2 (ble3_in4_en2 VSS VDD VSS VBN VBP) bitcell
bcell_ble3_in4_en2b (ble3_in4_en2b VDD VDD VSS VBN VBP) bitcell

bcell_ble3_in4_en3 (ble3_in4_en3 VSS VDD VSS VBN VBP) bitcell
bcell_ble3_in4_en3b (ble3_in4_en3b VDD VDD VSS VBN VBP) bitcell

bcell_ble3_in4_en4 (ble3_in4_en4 VSS VDD VSS VBN VBP) bitcell
bcell_ble3_in4_en4b (ble3_in4_en4b VDD VDD VSS VBN VBP) bitcell

bcell_ble4_in1_en1 (ble4_in1_en1 VSS VDD VSS VBN VBP) bitcell
bcell_ble4_in1_en1b (ble4_in1_en1b VDD VDD VSS VBN VBP) bitcell

bcell_ble4_in1_en2 (ble4_in1_en2 VSS VDD VSS VBN VBP) bitcell
bcell_ble4_in1_en2b (ble4_in1_en2b VDD VDD VSS VBN VBP) bitcell

bcell_ble4_in1_en3 (ble4_in1_en3 VSS VDD VSS VBN VBP) bitcell
bcell_ble4_in1_en3b (ble4_in1_en3b VDD VDD VSS VBN VBP) bitcell

bcell_ble4_in1_en4 (ble4_in1_en4 VSS VDD VSS VBN VBP) bitcell
bcell_ble4_in1_en4b (ble4_in1_en4b VDD VDD VSS VBN VBP) bitcell

bcell_ble4_in2_en1 (ble4_in2_en1 VSS VDD VSS VBN VBP) bitcell
bcell_ble4_in2_en1b (ble4_in2_en1b VDD VDD VSS VBN VBP) bitcell

bcell_ble4_in2_en2 (ble4_in2_en2 VSS VDD VSS VBN VBP) bitcell
bcell_ble4_in2_en2b (ble4_in2_en2b VDD VDD VSS VBN VBP) bitcell

bcell_ble4_in2_en3 (ble4_in2_en3 VSS VDD VSS VBN VBP) bitcell
bcell_ble4_in2_en3b (ble4_in2_en3b VDD VDD VSS VBN VBP) bitcell

bcell_ble4_in2_en4 (ble4_in2_en4 VSS VDD VSS VBN VBP) bitcell
bcell_ble4_in2_en4b (ble4_in2_en4b VDD VDD VSS VBN VBP) bitcell

bcell_ble4_in3_en1 (ble4_in3_en1 VSS VDD VSS VBN VBP) bitcell
bcell_ble4_in3_en1b (ble4_in3_en1b VDD VDD VSS VBN VBP) bitcell

bcell_ble4_in3_en2 (ble4_in3_en2 VSS VDD VSS VBN VBP) bitcell
bcell_ble4_in3_en2b (ble4_in3_en2b VDD VDD VSS VBN VBP) bitcell

bcell_ble4_in3_en3 (ble4_in3_en3 VSS VDD VSS VBN VBP) bitcell
bcell_ble4_in3_en3b (ble4_in3_en3b VDD VDD VSS VBN VBP) bitcell

bcell_ble4_in3_en4 (ble4_in3_en4 VSS VDD VSS VBN VBP) bitcell
bcell_ble4_in3_en4b (ble4_in3_en4b VDD VDD VSS VBN VBP) bitcell

bcell_ble4_in4_en1 (ble4_in4_en1 VSS VDD VSS VBN VBP) bitcell
bcell_ble4_in4_en1b (ble4_in4_en1b VDD VDD VSS VBN VBP) bitcell

bcell_ble4_in4_en2 (ble4_in4_en2 VSS VDD VSS VBN VBP) bitcell
bcell_ble4_in4_en2b (ble4_in4_en2b VDD VDD VSS VBN VBP) bitcell

bcell_ble4_in4_en3 (ble4_in4_en3 VSS VDD VSS VBN VBP) bitcell
bcell_ble4_in4_en3b (ble4_in4_en3b VDD VDD VSS VBN VBP) bitcell

bcell_ble4_in4_en4 (ble4_in4_en4 VSS VDD VSS VBN VBP) bitcell
bcell_ble4_in4_en4b (ble4_in4_en4b VDD VDD VSS VBN VBP) bitcell

ends CLB_N4

//Connection Box (Depends on Channel Width)
subckt Connectionbox (Input Output1 Output2 Output3 Output4 VDD VDDc VSS VBN VBP)
Ch1 (Input Mid1 VDD Bit1 VSS VBN VBP) TSSwitch
B1 (Bit1 VSS VDDc VSS VBN VBPC) bitcell
R1 (Mid1 Output1) resistor r=50
C1 (Output1 VSS) capacitor c=13f
Ch2 (Input Mid2 VDD Bit2 VSS VBN VBP) TSSwitch
B2 (Bit2 VSS VDDc VSS VBN VBPC) bitcell
R2 (Mid2 Output2) resistor r=50
C2 (Output2 VSS) capacitor c=13f
Ch3 (Input Mid3 VDD Bit3 VSS VBN VBP) TSSwitch
B3 (Bit3 VSS VDDc VSS VBN VBPC) bitcell
R3 (Mid3 Output3) resistor r=50
C3 (Output3 VSS) capacitor c=13f
Ch4 (Input Mid4 VDD Bit4 VSS VBN VBP) TSSwitch
B4 (Bit4 VSS VDDc VSS VBN VBPC) bitcell
R4 (Mid4 Output4) resistor r=50
C4 (Output4 VSS) capacitor c=13f
subckt ConnectionOutbox (Input Output Wire1 Wire2 Wire3 VDD VDDc VSS VBN VBP)
Ch (Input Mid1 VDD Bit1 VSS VBN VBP) TSSwitch
B (Bit1 VSS VDDc VSS VBN VBPC) bitcell
R (Mid1 Output1) resistor r=50
C (Output1 VSS) capacitor c=13f
W1 (Wire1 Mid1 VDD Bit2 VSS VBN VBP) TSSwitch
B1 (Bit2 VDDc VDDc VSS VBN VBPC) bitcell
R1 (Wire1 Output1) resistor r=50
C1 (Wire1 VSS) capacitor c=13f
W2 (Wire2 Mid1 VDD Bit2 VSS VBN VBP) TSSwitch
B2 (Bit2 VDDc VDDc VSS VBN VBPC) bitcell
R2 (Wire2 Output2) resistor r=50
C2 (Wire2 VSS) capacitor c=13f
W3 (Wire3 Mid1 VDD Bit2 VSS VBN VBP) TSSwitch
B3 (Bit2 VDDc VDDc VSS VBN VBPC) bitcell
R3 (Wire3 Output3) resistor r=50
C3 (Wire3 VSS) capacitor c=13f
ends Connectionbox

//Sense Amp (ASA w/o hysteresis)
subckt CSA1 (Input Output VDD VSS VBN VBP)
SA_EN (Input VSS VSS VBN) N_TRANSISTOR width=wn length=ldef
SA_N1 (X Input VSS VBN) N_TRANSISTOR width=wn length=ldef
SA_N2 (Output X D VBN) N_TRANSISTOR width=wn length=ldef
SA_N3 (D X VSS VBN) N_TRANSISTOR width=wn length=ldef
SA_P1 (A Input VDD VBP) P_TRANSISTOR width=wp length=ldef
SA_P2 (B Input A VBP) P_TRANSISTOR width=wp length=ldef
SA_P3 (C Input B VBP) P_TRANSISTOR width=wp length=ldef
SA_P4 (X Input C VBP) P_TRANSISTOR width=wp length=ldef
SA_P5 (Output X VDD VBP) P_TRANSISTOR width=wp length=ldef
ends CSA1

//Sense Amp (Joe's ASA)
subckt ASA (Input Output VDD VSS VBN VBP)
SA_EN (Input VSS VSS VBN) N_TRANSISTOR width=wn length=ldef
SA_N1 (X Input VSS VBN) N_TRANSISTOR width=wn length=ldef
SA_N2 (Output X D VBN) N_TRANSISTOR width=wn length=ldef
SA_N3 (D X VSS VBN) N_TRANSISTOR width=wn length=ldef
SA_P1 (A Input VDD VBP) P_TRANSISTOR width=wp length=ldef
SA_P2 (B Input A VBP) P_TRANSISTOR width=wp length=ldef
SA_P3 (C Input B VBP) P_TRANSISTOR width=wp length=ldef
SA_P4 (X Input C VBP) P_TRANSISTOR width=wp length=ldef
SA_P5 (Output X VDD VBP) P_TRANSISTOR width=wp length=ldef
SA_P6 (B X VSS VBP) P_TRANSISTOR width=wp length=ldef
ends ASA

//Bitcell
subckt bitcell (Bit BitBar VDD VSS VBN VBP)
P1 (BitBar Bit VDD VBP) P_TRANSISTOR width=wp length=ldef
P2 (Bit BitBar VDD VBP) P_TRANSISTOR width=wp length=ldef
N1 (BitBar Bit VSS VBN) N_TRANSISTOR width=wn length=ldef
N2 (Bit BitBar VSS VBN) N_TRANSISTOR width=wn length=ldef
ends bitcell

//FO4 Output
subckt FO4 (OUT VDD VSS VBN VBP)
FOUT1 (OUT OUTFO1 VDD VSS VBN VBP) Inv
FOUT2 (OUT OUTFO2 VDD VSS VBN VBP) Inv
FOUT3 (OUT OUTFO3 VDD VSS VBN VBP) Inv
FOUT4 (OUT OUTFO4 VDD VSS VBN VBP) Inv
ends FO4

//Net

